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Design Tools - Complete List

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Tool Namesort icon Last updated
RIVER: Reconfigurable Pre-Synthesized-Streaming Architecture for Signal Processing on FPGAs 07/04/2012 - 16:22
Register Management for Integrated Systems 06/05/2012 - 14:45
Refactoring for VHDL-AMS 03/30/2020 - 19:22
Redundant Via Insertion with Emphasis on Via Doubling above I/O Pins 10/26/2012 - 16:43
RcvASIP - FPGA Prototype of Flexible Heterogeneous multi-ASIP NoC-based Unified Turbo Receiver 03/30/2020 - 19:21
Ptolemy extension as Codesign Environment 04/18/2013 - 13:51
Prototypical Framework for Safe and Efficient Systems-on-Chip Design 07/04/2012 - 15:54
Property Coverage Checker 10/26/2012 - 16:43
PreMaDonna: Predictable Matching of Demands on Networked Architectures 10/26/2012 - 16:43
PowerMixer-IP - Power Analysis Framwork for SoC Designs 07/04/2012 - 15:05
PowerComposer Demo: Software-level Power Estimation for TI C5510 DSPs 10/26/2012 - 16:43
Power Optimization for Embedded sysTems 10/26/2012 - 16:43
Post Manufacture Variability Improvement Using Configurable Analogue Transistors (CATs) 04/18/2013 - 13:55
POLYSIGNAL 03/30/2020 - 19:22
Petrify 03/30/2020 - 18:57
PERFidiX 10/26/2012 - 16:43
PART-E 04/18/2013 - 16:13
OVPsim-FIM 01/14/2018 - 20:29
OTAWA, Open Tool for Adaptative WCET Analysis 10/26/2012 - 16:43
OS based Wireless Body Area Network for ECG 03/30/2020 - 19:55
OptiMMA - Optimization of MP-SoC Middleware for event-driven dynamic Applications 07/02/2012 - 10:42
Open-PEOPLE - Open - Power and Energy Optimization Platform and Estimator 09/09/2019 - 16:26
OneSpin 360 Module Verifier 04/18/2013 - 14:30
OneSpin 360 Module Verifier 04/18/2013 - 14:29
OneSpin 360 Equivalence Checker 04/18/2013 - 14:30
OneSpin 360 Equivalence Checker 04/18/2013 - 14:29
Nostrum Network-on-Chip Simulation Environment 10/26/2012 - 16:43
NOSTRUM 03/30/2020 - 19:22
NoC Synthesis Flow 10/26/2012 - 16:43
NoC on Graphics Processing Unit 01/02/2017 - 09:48
NEX: A Network Emulator boX to support the design of networked systems 04/22/2013 - 15:25
New approaches for solving polynomial equations 10/26/2012 - 16:43
neurocomm: Highly Integrated Packet-Based Communication in a Neuromorphic Wafer System 07/04/2012 - 16:28
Multiple simultaneous upset fault-tolerant FIR circuit design using delta-sigma modulation 03/30/2020 - 19:53
MultiLib 10/31/2012 - 10:18
MULTICON: Multiplierless Design of Low-Complexity and High-Speed DSP Systems 07/04/2012 - 16:36
MOVES: A Tool for Modelling and Verification of Embedded Systems 10/26/2012 - 16:43
MORPHEUS integrated toolset 11/30/2012 - 14:20
MoDES: Model Driven Development of Inteligent Embedded Systems 04/30/2013 - 19:02
Mission Level Design of Electronic Systems 10/26/2012 - 16:43
MIMO_SD_FEC demo: MIMO Detection-Decoding Engine 01/18/2014 - 21:32
Micro-profiler 10/26/2012 - 16:43
Methods and tools for synthesizing energy-efficient LCD bus interfaces 04/22/2013 - 15:24
MECS + DesParO - Hierarchical Simulation and Robust Design Aspects 07/04/2012 - 15:47
MBO - Optimizing memory testing architectures: the Memory Bist Optimizer 07/02/2012 - 10:40
MarciaTesta++: an automatic generator of assembly test programs for microprocessors’ data and instruction caches. 07/02/2012 - 10:38
Magnetic PDK - Magnetic Process Design Kit for Hybrid CMOS / Magnetic process 07/04/2012 - 15:14
MACT High-Level Synthesis 10/26/2012 - 16:43
Low Power Partial-Product Reduction-Tree Generator for Parallel Multipliers 10/26/2012 - 16:43
Lissom - ASIP Design in the Lissom Project 06/20/2012 - 12:49