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| Tool Name | Author(s) | Last updated |
|---|---|---|
| Dynamic Virtual Analyzer and Simulator |
Madsen, Jan Hasan Baig, DTU C... |
03/30/2020 - 18:38 |
| NoC Synthesis Flow | 10/26/2012 - 16:43 | |
| GAUT: High-Level Synthesis Tool (from C/C++ to RTL) |
Dominique Heller Dr. Pierre Bomel (pierre.bomel@univ-ubs.fr) Philippe Coussy, ... |
09/09/2019 - 18:13 |
| Bist for RAm IN Seconds | 10/26/2012 - 16:43 | |
| FoREnSiC: An Automatic Debugging Environment for C Programs |
Georg Hofferek (Graz University of Technology) Robert Könighofer (Graz University of Technology) Jaan Raik (Tallinn University of Technology) Alexander Finder (University of Bremen) Görschwin Fey (University of Bremen) Urmas Repinski (Tallinn University of Technology) Rolf Drechsler (University of Bremen) André Sülflow (University of Bremen) Roderick Bloem (Graz University of Technology) - -, -, DE |
07/04/2012 - 16:19 |
| DECIDER: Test and Verification at the Register-Transfer Level | 10/26/2012 - 16:43 | |
| VintAge - A simulation framework for the assessment of NBTI-induced aging effects in SoC designs |
Giulio Gambardella (Politecnico di Torino) Daniele Rolfo (Politecnico di Torino) Massimo Poncino (Politecnico di Torino) - -, -, IT |
07/04/2012 - 15:10 |
| An ESL Workbench for early MPSoC Design Space Exploration | 04/18/2013 - 16:14 | |
| Nostrum Network-on-Chip Simulation Environment | 10/26/2012 - 16:43 | |
| Hardware/software architecture of an algorithm for vision-based real-time vehicle detection in dark environments | 10/26/2012 - 16:43 |
