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| Tool Name | Author(s) | Last updated |
|---|---|---|
| Dynamic Virtual Analyzer and Simulator |
Madsen, Jan Hasan Baig, DTU C... |
03/30/2020 - 17:38 |
| GAUT: High-Level Synthesis Tool (from C/C++ to RTL) |
Dominique Heller Dr. Pierre Bomel (pierre.bomel@univ-ubs.fr) Philippe Coussy, ... |
09/09/2019 - 17:13 |
| GSNOC - A Generic Scalable Simulation Framework for 3-Dimension Networks-on-Chip |
Ashok Jaiswal (Darmstadt University of Technology) Philip Gottschling (Darmstadt University of Technology) Thomas Hollstein (Tallinn University of Technology) Klaus Hofmann (Darmstadt University of Technology) - -, -, DE |
07/04/2012 - 14:53 |
| WSN Energy Harvesting - Monitoring and Control of a Dynamically Reconfigurable Wireless Sensor Node Powered by Hybrid Energy Harvesting |
Faizal Arya Samman (TU Darmstadt) Manfred Glesner (TU Darmstadt) Ping Zhao (TU Darmstadt) - -, -, DE |
07/04/2012 - 14:19 |
| LambdaChartExplorer: System Level EDA via Lambda Chart Exploration |
- -, -, DE |
07/04/2012 - 15:09 |
| GeneralStore | 06/05/2012 - 17:13 | |
| Hardware-in-the-Loop Simulations with Matlab/Simulink/ModelSim for FPGA based designflows | 04/18/2013 - 11:16 | |
| ID.Fix - Infrastructure for the design of fixed-point systems |
Daniel MENARD (IRISA - INRIA) Quentin Meunier (INRIA) Olivier Sentieys (IRISA - INRIA) - -, -, FR |
07/04/2012 - 14:09 |
| RcvASIP - FPGA Prototype of Flexible Heterogeneous multi-ASIP NoC-based Unified Turbo Receiver |
Atif Raza Jafri (Institut Telecom; Telecom Bretagne; Lab-STICC) Amer Baghdadi (Institut Telecom; Telecom Bretagne; Lab-STICC) Michel Jézéquel (Institut Telecom; Telecom Bretagne; Lab-STICC) - -, -, FR |
03/30/2020 - 18:21 |
| SystemC Environment | 03/30/2020 - 18:23 |
