Recent and emerging wireless standards impose stringent requirements in terms of high throughput, error rate performance and flexibility. Although turbo processing in the receiver ensures error rate performance close to theoretical limits, due to its iterative nature, it creates a bottleneck in achieving high throughput. On the hardware side, the high throughput dedicated architectures can not cope with the flexibility requirements hence some programmable, yet high throughput, architecture is mandatory for future wireless terminals. To address the three stated issues we are demonstrating FPGA prototype of a parallel, flexible and high throughput heterogeneous multi-ASIP NoC-based unified turbo receiver. The proposed prototype can be configured for required parameters by changing application programs of constituent ASIPs and one can extract required processing power by using adequate number of ASIP elements.