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RIVER: Reconfigurable Pre-Synthesized-Streaming Architecture for Signal Processing on FPGAs

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Tool Name (abbreviation): 
RIVER architecture
Author(s): 
- -, -, DE
(unregistered) Author(s): 
Christian Brugger (KIT)
Matthias Balzer (KIT)

We present a scalable run-time configurable and programmable signal processing architecture for real-time applications which covers a wide performance spectrum. For evaluation and design space exploration we have developed a highly configurable FPGA implementation. Our approach goes beyond conventional special purpose signal processing engines. We base our novel architecture on programmable components which can be re-combined and re-configured to match application specific requirements for signal processing tasks. Our framework supports and extends scalability through a massive repository of pre-synthesized and optimized FPGA configurations. This feature is crucial for applications where design changes must be instant. Furthermore, our framework shields users from HDL design flows and manual design optimization. However, we do not impede architectural changes but provide support for them through custom instructions and numerous design time options. Our results suggest that our architecture performs well for computational- and memory-intensive kernels.

Project Information
Project Acronym: 
River Architecture, Dynamic Streaming Engine (DSE)
Project Start: 
Mon, 08/01/2011
Project End: 
Fri, 08/31/2012
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Keywords: 
FPGA
image processing
Reconfigurable
multi-core
streaming