We introduce a systematic power analysis framework for SoC designs using bottom-up power modeling integrated with top-down power estimation. Four power analysis tools have been realized: (1) PowerBrick, a power characterization tool to construct power libraries for standard cell library and memory compiler, (2) PowerMixer, an RTL/gate-level power estimator for large logic design, (3) PowerMixerIP, an IP-based power model builder to build power models for general IPs as well as processor IPs, and (4) PowerDepot, an ESL power estimation tool to enable super-fast system-level SoC power estimation. Equipped with these highly automatic tools, one is able to drastically reduce the effort and time spent in building the power analysis environment for SoC designs.