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A Configurable Platform for Embedded Systems |
10/26/2012 - 16:43 |
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SC-VERIFIER |
10/26/2012 - 16:43 |
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Yield Estimation Tool Considering Via Failures |
10/26/2012 - 16:43 |
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Test chip and dedicated data acquisition system for reliability study of high current first level interconnections |
10/26/2012 - 16:43 |
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The Coffee framework: COmpiler Framework for Energy-aware Exploration |
10/26/2012 - 16:43 |
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The Power Analysis Tool for an Embedded Systems Development Board |
10/26/2012 - 16:43 |
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Topas |
10/26/2012 - 16:43 |
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Bounded Model Checker Using Property Based Automated Abstractions |
10/26/2012 - 16:43 |
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New approaches for solving polynomial equations |
10/26/2012 - 16:43 |
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SystemCASS |
10/26/2012 - 16:43 |
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Workcraft: a static data flow structure editing, visualisation and analysis tool |
10/26/2012 - 16:43 |
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An Academic High-Level Synthesis Tool for Control and Memory Intensive Applications |
10/26/2012 - 16:43 |
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Turbo Tester |
10/26/2012 - 16:43 |
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BESST tool kit: VERIMAP |
10/26/2012 - 16:43 |
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BESST tool kit: VERISAT |
10/26/2012 - 16:43 |
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BESST tool kit: VERISYN |
10/26/2012 - 16:43 |
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A Hardwired H.264/AVC Main Profile Video Decoder Prototype |
10/26/2012 - 16:43 |
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Lance Compiler Frontend |
10/31/2012 - 10:05 |
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MultiLib |
10/31/2012 - 10:18 |
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YARDstick: Automation tool for custom processor development |
10/31/2012 - 13:09 |
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An ASIP Design Environment |
10/31/2012 - 13:22 |
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General Purpose VLIW Processor for Multiband-Multistandard applications |
11/30/2012 - 13:39 |
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MORPHEUS integrated toolset |
11/30/2012 - 14:20 |
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Analoge Struktursynthese anhand eines Operationsverstärkers |
11/30/2012 - 15:27 |
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Daedalus^RT: The System-Level Design Flow for Hard-Real-Time Embedded MPSoCs Platforms |
12/21/2012 - 18:55 |
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C++TESK Testing ToolKit |
12/27/2012 - 10:46 |
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SYNAPS, New developments in solution of systems of polynomial |
04/18/2013 - 11:24 |
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A lightweight and remote partially reconfigurable platform |
04/18/2013 - 11:31 |
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A mixed (hardware and software) rapid prototyping platform. |
04/18/2013 - 11:33 |
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µSPIDER CAD TOOL: CASE STUDY OF NOC IP GENERATION FOR FPGA |
04/18/2013 - 11:34 |
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A verification environment for high-level designs based on system dependence graphs |
04/18/2013 - 11:35 |
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A System-level MPSoC Simulation Framework |
04/18/2013 - 11:49 |
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Hardware-in-the-Loop Simulations with Matlab/Simulink/ModelSim for FPGA based designflows |
04/18/2013 - 12:16 |
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System-Level Design Tool |
04/18/2013 - 13:26 |
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Ptolemy extension as Codesign Environment |
04/18/2013 - 13:51 |
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Post Manufacture Variability Improvement Using Configurable Analogue Transistors (CATs) |
04/18/2013 - 13:55 |
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SDF3 |
04/18/2013 - 13:56 |
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Trust-by-Wire in Packet-switched IP Networks: Calling Line Identification Presentation for IP |
04/18/2013 - 14:01 |
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High-level C-Compilerframework ICD-C |
04/18/2013 - 14:24 |
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OneSpin 360 Equivalence Checker |
04/18/2013 - 14:29 |
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OneSpin 360 Module Verifier |
04/18/2013 - 14:29 |
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OneSpin 360 Module Verifier |
04/18/2013 - 14:30 |
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OneSpin 360 Equivalence Checker |
04/18/2013 - 14:30 |
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Cycle-accurate simulation of object oriented descriptions for runtime-reconfigurable systems |
04/18/2013 - 16:09 |
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PART-E |
04/18/2013 - 16:13 |
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An ESL Workbench for early MPSoC Design Space Exploration |
04/18/2013 - 16:14 |
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SoftExplorer: a Software Power/energy Consumption Estimation Tool |
04/18/2013 - 16:19 |
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Configuration Tool and FPGA-Prototype of a Hardware Packet Processing System |
04/22/2013 - 15:19 |
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LANCE Retargetable C Compiler |
04/22/2013 - 15:21 |
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SHINE: FPGA prototyping of SpaceWire IP cores for High Data Rate and Fault Tolerant Invehicle Networking |
04/22/2013 - 15:22 |
