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BESST tool kit: VERISYN

Fri, 10/26/2012 - 16:43 — Andreas Vörg, eda...
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(unregistered) Author(s): 
Frank Burns
Delong Shang
Alex Yakovlev
Download URL: 
http://async.org.uk/besst/
Homepage: 
https://www.rd-access.eu/edatools/system/files/ubooth_submission/2005/Descriptio...

High-level scheduling and splitting the system into control and data paths, using Petri Nets (PNs) for intermediate representation (VeriSyn tool).

Publications:
D. Shang, F.Burns, A.Koelmans, A.Yakovlev, F. Xia. Asynchronous system synthesis based on direct mapping using VHDL and Petri nets, IEE Proceedings-CDT, Vol. 151, No.3, May 2004, pp. 209-220.

Contact:
Frank Burns (f.p.burns@ncl.ac.uk)

Project Information
Project Acronym: 
BESST
Project Homepage: 
http://async.org.uk/besst/
Project Description: 
Behavioural Synthesis of Systems with Heterogeneous Timing:


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