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Evolvable Hardware FPGA-based platform for Autonomous Fault-tolerant Systems |
07/04/2012 - 16:43 |
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WCDMA DPD ADC: Optimizing and validating high level design parameters of ADC for digital predistortion in base stations |
10/01/2012 - 19:36 |
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COMPLEX_UML_MARTE: The COMPLEX Eclipse Framework for UML/MARTE Specification of Embedded Systems and Automatic Generation of Executable Models for Design Space Exploration |
10/01/2012 - 19:37 |
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FlexFilm: Real-time digital film processing with a FPGA-based reconfigurable platform |
10/02/2012 - 01:00 |
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CoMPSoC: Virtual Platforms for Energy Efficient Execution of Mixed Time-Criticality Applications |
10/02/2012 - 11:38 |
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Analog Circuits: Explorative Synthesis of Topologies |
10/02/2012 - 17:34 |
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Fast Distributed Property Checking |
10/02/2012 - 18:24 |
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CλaSH - Functional Hardware Design in CλaSH |
10/11/2012 - 06:12 |
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CRISP - A dynamically reconfigurable many-core platform for streaming applications. |
10/11/2012 - 06:15 |
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A broadband FFT-Spectrometer at work |
10/26/2012 - 16:43 |
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Advances in Symbolic Performance Analysis |
10/26/2012 - 16:43 |
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BESST tool kit: CONFRES |
10/26/2012 - 16:43 |
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Constraint-Engineering-System |
10/26/2012 - 16:43 |
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Coplan for ADS |
10/26/2012 - 16:43 |
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DECIDER: Test and Verification at the Register-Transfer Level |
10/26/2012 - 16:43 |
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Design Cost Controlling |
10/26/2012 - 16:43 |
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BESST tool kit |
10/26/2012 - 16:43 |
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Bist for RAm IN Seconds |
10/26/2012 - 16:43 |
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Formal Verification of Design Properties of Hardware Architectures |
10/26/2012 - 16:43 |
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ENHANCEMENTS OF STATECHART-MODELING—
THE KIEL ENVIRONMENT |
10/26/2012 - 16:43 |
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Micro-profiler |
10/26/2012 - 16:43 |
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Mission Level Design of Electronic Systems |
10/26/2012 - 16:43 |
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MOVES: A Tool for Modelling and Verification of Embedded Systems |
10/26/2012 - 16:43 |
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Nostrum Network-on-Chip Simulation Environment |
10/26/2012 - 16:43 |
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Hardware/software architecture of an algorithm for vision-based real-time vehicle detection in dark environments |
10/26/2012 - 16:43 |
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Co-simulation tools for Networked Embedded Systems |
10/26/2012 - 16:43 |
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IPWM |
10/26/2012 - 16:43 |
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Low Power Partial-Product Reduction-Tree Generator for Parallel Multipliers |
10/26/2012 - 16:43 |
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MACT High-Level Synthesis |
10/26/2012 - 16:43 |
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PERFidiX |
10/26/2012 - 16:43 |
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BESST tool kit: PN2DC |
10/26/2012 - 16:43 |
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Power Optimization for Embedded sysTems |
10/26/2012 - 16:43 |
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BESST tool kit: OPTIMIST |
10/26/2012 - 16:43 |
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OTAWA, Open Tool for Adaptative WCET Analysis |
10/26/2012 - 16:43 |
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Property Coverage Checker |
10/26/2012 - 16:43 |
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Using dynamically reconfigurable instruction set architecture processor for SoC |
10/26/2012 - 16:43 |
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A SoC Design Platform |
10/26/2012 - 16:43 |
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Redundant Via Insertion with Emphasis on Via Doubling above I/O Pins |
10/26/2012 - 16:43 |
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A SystemC model generator |
10/26/2012 - 16:43 |
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PowerComposer Demo: Software-level Power Estimation for TI C5510 DSPs |
10/26/2012 - 16:43 |
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PreMaDonna: Predictable Matching of Demands on Networked Architectures |
10/26/2012 - 16:43 |
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Versatile SoC Development Environment Supporting HW/SW Co-Design And Mixed Abstraction-level Simulation |
10/26/2012 - 16:43 |
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Submarine Explorer – A low cost AUV |
10/26/2012 - 16:43 |
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A NoC Synthesis and Floorplan Flow |
10/26/2012 - 16:43 |
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NoC Synthesis Flow |
10/26/2012 - 16:43 |
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A Configurable Platform for Embedded Systems |
10/26/2012 - 16:43 |
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SC-VERIFIER |
10/26/2012 - 16:43 |
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SiSMA: Simulator for Statistical Mismatch Analysis |
10/26/2012 - 16:43 |
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SoC Architecture Explorer |
10/26/2012 - 16:43 |
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Specification data gathering |
10/26/2012 - 16:43 |
