BRAINS: To minimize the test effort, we present an automatic generation framework of memory built-in self-test (BIST) cores and test integration platform for SOC designs. Test integration of heterogeneous memory architectures and clusters of memories are focused. The automatic test grouping and scheduling optimize the overhead in test time, performance, power consumption, etc.

Projects:
Name of the project: NTHU Network Security Processor and the Related SOC Design and Test Technologies Leader: Prof. Cheng-Wen Wu E-mail: cww@ee.nthu.edu.tw Internet address: http://larc.ee.nthu.edu.tw/~jcyeh/Proj/DFT/ Project partner: IC DTC, VLSI/CAD Lab, NTHU Start of the project: 2002/06/01 End of the project: 2005/08/31

Contact:
Li-Ming Denq (lmdenq@slugger.ee.nthu.edu.tw)