The BESST tool kit is used for asynchronous system synthesis based on Petri Nets. It incorporates software tools for high-level partitioning, scheduling, direct mapping and logic synthesis. These are used to generate efficient speed-independent circuits from behavioural Verilog specification.

Publications:
www.staff.ncl.ac.uk/alex.yakovlev/home.formal/besst/IGR-BESST.pdf

Contact:
Alex Yakovlev (alex.yakovlev@ncl.ac.uk)