MultiLib |
10/31/2012 - 10:18 |
Lance Compiler Frontend |
10/31/2012 - 10:05 |
BESST tool kit: VERIMAP |
10/26/2012 - 16:43 |
BESST tool kit: VERISAT |
10/26/2012 - 16:43 |
BESST tool kit: VERISYN |
10/26/2012 - 16:43 |
A Hardwired H.264/AVC Main Profile Video Decoder Prototype |
10/26/2012 - 16:43 |
Workcraft: a static data flow structure editing, visualisation and analysis tool |
10/26/2012 - 16:43 |
An Academic High-Level Synthesis Tool for Control and Memory Intensive Applications |
10/26/2012 - 16:43 |
Turbo Tester |
10/26/2012 - 16:43 |
New approaches for solving polynomial equations |
10/26/2012 - 16:43 |
SystemCASS |
10/26/2012 - 16:43 |
Yield Estimation Tool Considering Via Failures |
10/26/2012 - 16:43 |
Test chip and dedicated data acquisition system for reliability study of high current first level interconnections |
10/26/2012 - 16:43 |
The Coffee framework: COmpiler Framework for Energy-aware Exploration |
10/26/2012 - 16:43 |
The Power Analysis Tool for an Embedded Systems Development Board |
10/26/2012 - 16:43 |
Topas |
10/26/2012 - 16:43 |
Bounded Model Checker Using Property Based Automated Abstractions |
10/26/2012 - 16:43 |
SC-VERIFIER |
10/26/2012 - 16:43 |
SiSMA: Simulator for Statistical Mismatch Analysis |
10/26/2012 - 16:43 |
SoC Architecture Explorer |
10/26/2012 - 16:43 |
Specification data gathering |
10/26/2012 - 16:43 |
Soc TEst Aid Console |
10/26/2012 - 16:43 |
System Tuning Shell: A Design Space Exploration Tool |
10/26/2012 - 16:43 |
Submarine Explorer – A low cost AUV |
10/26/2012 - 16:43 |
A NoC Synthesis and Floorplan Flow |
10/26/2012 - 16:43 |
NoC Synthesis Flow |
10/26/2012 - 16:43 |
A Configurable Platform for Embedded Systems |
10/26/2012 - 16:43 |
PowerComposer Demo: Software-level Power Estimation for TI C5510 DSPs |
10/26/2012 - 16:43 |
PreMaDonna: Predictable Matching of Demands on Networked Architectures |
10/26/2012 - 16:43 |
Versatile SoC Development Environment Supporting HW/SW Co-Design And Mixed Abstraction-level Simulation |
10/26/2012 - 16:43 |
Using dynamically reconfigurable instruction set architecture processor for SoC |
10/26/2012 - 16:43 |
A SoC Design Platform |
10/26/2012 - 16:43 |
Redundant Via Insertion with Emphasis on Via Doubling above I/O Pins |
10/26/2012 - 16:43 |
A SystemC model generator |
10/26/2012 - 16:43 |
OTAWA, Open Tool for Adaptative WCET Analysis |
10/26/2012 - 16:43 |
Property Coverage Checker |
10/26/2012 - 16:43 |
PERFidiX |
10/26/2012 - 16:43 |
BESST tool kit: PN2DC |
10/26/2012 - 16:43 |
Power Optimization for Embedded sysTems |
10/26/2012 - 16:43 |
BESST tool kit: OPTIMIST |
10/26/2012 - 16:43 |
IPWM |
10/26/2012 - 16:43 |
Low Power Partial-Product Reduction-Tree Generator for Parallel Multipliers |
10/26/2012 - 16:43 |
MACT High-Level Synthesis |
10/26/2012 - 16:43 |
Micro-profiler |
10/26/2012 - 16:43 |
Mission Level Design of Electronic Systems |
10/26/2012 - 16:43 |
MOVES: A Tool for Modelling and Verification of Embedded Systems |
10/26/2012 - 16:43 |
Nostrum Network-on-Chip Simulation Environment |
10/26/2012 - 16:43 |
Hardware/software architecture of an algorithm for vision-based real-time vehicle detection in dark environments |
10/26/2012 - 16:43 |
Co-simulation tools for Networked Embedded Systems |
10/26/2012 - 16:43 |
ENHANCEMENTS OF STATECHART-MODELING—
THE KIEL ENVIRONMENT |
10/26/2012 - 16:43 |