Skip to Content

Functional Verification

Dynamic Virtual Analyzer and Simulator

Tool Name (abbreviation): 
D-VASim
Author(s): 
Hasan Baig, DTU C...
(unregistered) Author(s): 
Madsen, Jan
Screenshot: 

D-VASim (Dynamic Virtual Analyzer and simulator) is a tool to analyze and simulate the genetic logic circuit models developed in the Systems Biology Mark-up Language (SBML).

Project Information
Project Acronym: 
D-VASim
Project Start: 
Fri, 08/15/2014
Project End: 
Fri, 03/11/2016
Tag your tool
Keywords: 
D-VASim
Genetic logic circuits
SBML
Systems biology
synthetic biology
genetic circuits
stochastic simulation
deterministic simulation
Categorize your Tool: 
Prototype
DATE
University Booth
Design Automation Methodology
Concept Engineering
Test Specification
Prototyping
Verification
Functional Verification
Simulation
Test Verification
Accuracy Evaluation
analysis
Biological Information Sensing System
CAD
CAD Tool
computation
Computer aided design
D-VASim
deterministic simulation
genetic circuits
Genetic logic circuits
Graphic User Interface (GUI)
run-time
SBML
Simulation-Based Verification
software verification
stochastic simulation
synthetic biology
Demonstration
Development
Released
Knowledge and Education
Training
Research Institute

C++TESK Testing ToolKit

Tool Name (abbreviation): 
C++TESK
Author(s): 
- -, -, RU
- -, -, RU

C++TESK Testing ToolKit is an open-source C++ based toolkit intended for automated functional testing of software components (mostly in C/C++) and RTL (HDL) models of digital hardware (in Verilog and VHDL). The main part of the toolkit is a library of C++ classes and macros that define facilities for constructing formal specifications (reference models), adapters of components under test, test scenarios and test coverage metrics. Basing on C++ descriptions provided by a user, a test system is compiled.

Project Information
Project Acronym: 
C++TESK Testing ToolKit
Project Start: 
Tue, 06/01/2010
Project Description: 
C++TESK Testing ToolKit combines results of the following ISPRAS's projects: C++TESK (creation of formal specifications, test scenarios and test coverage metrics by means of C++ programming language), C++TESK Hardware Edition (development of reference models of hardware designs and C++-RTL adapters), CTESK (automated generation of test sequences using graph exploration techniques), Distributed FSM (tests parallelization on computer networks and clusters) and Aspectrace (test event tracing and report generation). The project also depends on VeriTool (generation of C/C++ API for Verilog modules), which in turn depends on Icarus Verilog.
Tag your tool
Keywords: 
Simulation-Based Verification
Model-Based Testing
Hardware Modeling
Categorize your Tool: 
Transaction Level Modelling (TLM)
University Booth
Functional Verification
Beta
Research Institute
Syndicate content