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Simulation

NoC on Graphics Processing Unit

Tool Name (abbreviation): 
NOCOGIRI
Project Information
Project Acronym: 
NoCoGiRi
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ASPDAC
DATE
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Simulation
3D NoC
MP-SoC
MPSoC
multi-core
multicore
NoC
System-on-Chip

Dynamic Virtual Analyzer and Simulator

Tool Name (abbreviation): 
D-VASim
Author(s): 
Hasan Baig, DTU C...
(unregistered) Author(s): 
Madsen, Jan
Screenshot: 

D-VASim (Dynamic Virtual Analyzer and simulator) is a tool to analyze and simulate the genetic logic circuit models developed in the Systems Biology Mark-up Language (SBML).

Project Information
Project Acronym: 
D-VASim
Project Start: 
Fri, 08/15/2014
Project End: 
Fri, 03/11/2016
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Keywords: 
D-VASim
Genetic logic circuits
SBML
Systems biology
synthetic biology
genetic circuits
stochastic simulation
deterministic simulation
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Prototype
DATE
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Design Automation Methodology
Concept Engineering
Test Specification
Prototyping
Verification
Functional Verification
Simulation
Test Verification
Accuracy Evaluation
analysis
Biological Information Sensing System
CAD
CAD Tool
computation
Computer aided design
D-VASim
deterministic simulation
genetic circuits
Genetic logic circuits
Graphic User Interface (GUI)
run-time
SBML
Simulation-Based Verification
software verification
stochastic simulation
synthetic biology
Demonstration
Development
Released
Knowledge and Education
Training
Research Institute
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