Skip to Content

Synthesis

A Data-driven Synchronous Elastic Synthesiser

Tool Name (abbreviation): 
eTeak
Author(s): 
Mahdi Jelodari Ma...

eTeak is a high-level synthesis EDA, that aims to generate Globally Asynchronous Locally Synchronous (GALS) SoCs from a timing-free description. eTeak is a synchronous extension to the Teak Synthesis system which is a dataflow backend for the Balsa language. eTeak adopts Synchronous Elastic Protocol to provide a common timing behaviour in the computation and communication domains. This work is a part of The GAELS project supported by EPSRC under research grant EP/I038306/1.

Project Information
Project Acronym: 
GAELS
Project Start: 
Sat, 01/01/2011
Project End: 
Thu, 12/31/2015
Project Funding ID: 
EPSRC - The University of Manchester (PhD Scholarship)
Tag your tool
Categorize your Tool: 
Abstraction Level of Electronic Systems
Architecture Design
Conferences
ASPDAC
DAC
DATE
University Booth
Design Automation Methodology
Specification
Implementation
Synthesis
CAD
CAD Tool
EDA
FPGAs
High-Level Synthesis
Low Power

GAUT: High-Level Synthesis Tool (from C/C++ to RTL)

Tool Name (abbreviation): 
GAUT
Author(s): 
Philippe Coussy, ...
(unregistered) Author(s): 
Dominique Heller
Dr. Pierre Bomel (pierre.bomel@univ-ubs.fr)

 GAUT is an open source High-Level Synthesis tool. From a bit-accurate C/C++ specification it automatically generates a pipelined RTL architecture described in VHDL and SystemC simulation models (TLM and CABA).

Tag your tool
Keywords: 
High-Level Synthesis; ESL; EDA; FPGA; ASIC; SoC; hardware design; RTL; SystemC; TLM; DSE; CAD; GCC
Categorize your Tool: 
Prototype
Design Automation Methodology
Synthesis
Syndicate content