We demonstrate concurrent execution of a data intensive, soft real time graphics application and a latency sensitive control application on the same multicore. These applications share an SDRAM with a “faulty” application trying to corrupt their behavior by trying to write into their memory and to aggressively occupy the memory bus. We show that traditional techniques (e.g. Round Robin, TDMA) either do not produce correct behavior or have poor performance, while our approach ensures both. Hardware: We will present the demo on an Altera Cyclone III Development Board using NIOS II processors.