Our eClock provides you a pure cell‐based and all‐digital based ADPLL, which has the better noisy immunity and the higher stability as compared to analog ones. Moreover, eClock can simplify all tasks associated with ADPLL design allowing the user to get a high performance, cost effective design in a much easier way. By simply selecting a target process technology and defining the reference and output clocks, eClock will search quickly to find one configuration to meet your specification with almost minimum area cost. The silicon measurement results show that this is indeed a promising new alternative for analog PLLs, especially for advanced nanometer technologies.