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Automated metal interconnect structure generation

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(unregistered) Author(s): 
Matthias Harter

The software consists of a setup of parasitic extraction tools and a script, written in the Cadence SKILL language, to automatically generate 3D metal interconnect structures, to perform parasitic extraction with all of thetools and to store the parasitic values in a file for analysis. The analysis then provides information about the different tool performance and accuracy.

Contact:
Matthias Harter (harter@uni-mannheim.de)

Project Information
Project Acronym: 
SEED
Project Description: 
Support of Education in Electronic Design: SEED2002 is a university/industry collaboration to enhance and reform the education in the field of semi-custom/full-custom ASIC design at the Universities of Mannheim, Heidelberg and Kaiserslautern, Germany. With this project Cadence Design Systems enables us to teach leading-edge ASIC design using their most innovative products. Beginning with this semester (mid of october to mid of february) we (Computer Architecture Group, University of Mannheim) teach a lecture and a practical course named 'Semi-Custom Design Flow' (SCDF), where our students learn the methodology of high-speed nanometer ASIC design by the use of the most innovative EDA tools. These include Physically Knowledgeable Synthesis (PKS), FirstEncounter, Nanoroute, CeltIC and Fire&Ice supported by Cadence Design Systems. This lecture and practical course affiliates perfectly to the lecture 'hardware design', that has been held for years now and covers (architectural) system, interface and digital circuit design using Verilog HDL. Like the afore mentioned lecture and practical course 'Semi-Custom Design Flow' all participating universities are going to introduce new lectures and courses or restructure existing ones in the way that the whole design flow is covered. The main focus during this work is to develop practical exercises suitable for student work but also complex enough to face the problems of real-world designs. Missing tool experience is compensated by experts from Cadence VCAD Services in Feldkirchen, Germany. The expertise of the participating groups define the advanced subject course curriculum. It ranges from the afore mentioned: * high-level system and interface design, * synthesis, place and route, extraction, static timing analysis (the whole cell-based design flow), * to full custom analog and standard cell design and * the integration of both worlds by timing, power and functional characterization and abstract generation. By virtually integrating Cadence engineers into our Computer Aided Design ("CAD") activities, we will benefit not only from the experience of the specific engineers, but also from a direct channel to Cadence's know-how network. This will typically result in a more reliable design environment designed for flexibility and also in a faster and smoother integration of technology enhancements. For us, this will provide the possibility of designing higher quality designs, within shorter design cycles. The SEED2002 project was initiated by the Computer Architecture Group, University of Mannheim.