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ADHAM: Adaptive Heap Management on Many-Core Platforms

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Tool Name (abbreviation): 
ADHAM
Author(s): 
- -, -, GR
(unregistered) Author(s): 
Alex Bartzas (National Technical University of Athens / ICCS)
Dimitrios Soudris (National Technical University of Athens / ICCS)

Memory management is one of the key challenges in the design of computing systems where the memory is often the main bottleneck. The problem scales disproportionally as new systems are based on many-core architectures where the cores have to struggle accessing a limited amount of resources. Moreover, the excessive variations of modern systems, both in hardware and in software, makes necessary the usage of dynamic memory management (DMM) mechanisms. Extensive research has been conducted for general-purpose DMM, which targets single processor or multi-processor domain. However, the inherent generality of existing DMM eliminates the potential for customization optimizations. In this work, we present dmmlib, a highly portable DMM library written in C. It allows developers to generate custom heap managers by choosing the desired features and policies. The framework provides custom implementations for dynamic memory allocation, re-allocation and de-allocation which could replace classic system calls, i.e. malloc(), realloc() and free(). Multi-thread DMM can be supported by using POSIX mutexes or platform-specific synchronization primitives. The memory can be organized in a multiple number of heaps, each of which may contain or not lists of fixed-sized free blocks. The designer using the dmmlib can generate an application-specific and adaptive heap manager, being able to automatically reconfigure itself at runtime taking into consideration memory fragmentation and footprint variations and the availability of memory resources. In the context of this work the dmmlib framework is integrated in ST Platform 2012. It is shown that dmmlib could save on average 62% of the total cycles spent on memory resource management compared to P2012’s current memory allocator without increasing the allocator’s overhead.

Project Information
Project Acronym: 
2PARMA
Project Start: 
Fri, 01/01/2010
Project End: 
Mon, 12/31/2012
Project Funding ID: 
FP7-ICT-2009-4-248716
Project Description: 
The current trend in computing architectures is to replace complex superscalar architectures with small homogeneous processing units connected by an on-chip network. This trend is mostly dictated by inherent silicon technology frontiers, which are getting as closer as the process densities levels increase. The number of cores to be integrated in a single chip is expected to rapidly increase in the coming years, moving from multi-core to many-core architectures. This trend will require a global rethinking of software and hardware design approaches. This class of computing systems (Many-core Computing Fabric) promises to increase performance, scalability and flexibility if appropriate design and programming methodologies will be defined to exploit the high degree of parallelism exposed by the architecture. Other potential benefits of Many-core Computing Fabric include energy efficiency, improved silicon yield, and accounting for local process variations. To exploit these potential benefits, effective run-time power and resource management techniques are needed. With respect to conventional computing architectures, Many-core Computing Fabric offers some customisation capabilities to extend and/or configure at run-time the architectural template to address a variable workload. The 2PARMA project aims at overcoming the lack of parallel programming models and run-time resource management techniques to exploit the features of many-core processor architectures. To this purpose, a proper Consortium has been set up to gather the required expertise in the areas of system/application software and computing architectures. The 2PARMA project focuses on the definition of a parallel programming model combining component-based and single-instruction multiple-thread approaches, instruction set virtualisation based on portable bytecode, run-time resource management policies and mechanisms as well as design space exploration methodologies for Many-core Computing Fabrics.
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Keywords: 
Heap Management
Adaptive
Many-Core Architectures