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A Platform for Multi-Language Mixed-Signal Simulation

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(unregistered) Author(s): 
Hamidreza Ghasemi
Amir Masoud Gharehbaghi
Arezoo Kamran
Ali Shahabi
Zainalabedin Navabi

Mixed-Signal Simulator is a mixed-signal, mixed-domain, and mixed-language design environment which supports VHDL-AMS 1999, VHDL-2002, Verilog 2001, SystemVerilog 2005 assertions, and SystemC 2005.

Contact:
Parisa Razaghi (m.sedghi@ece.ut.ac.ir)

Project Information
Project Description: 
SystemC Transaction Level Synthesis: