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A High-Speed Dynamic Reconfigurable Multilevel Parallel Architecture

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(unregistered) Author(s): 
D. Kissler
H. Dutta
A. Kupriyanov
F. Hannig
J. Teich

The CoMap project investigates the holistic co-design of a new class of highly parameterizable, massively parallel processor architectures. This architecture type is called weakly programmable processor arrays (WPPAs). Two DSP algorithms were implemented with the help of dynamic reconfiguration on the same WPPA hardware, prototyped on FPGA.

Contact:
Dmitrij Kissler (Kissler@cs.fau.de)