Skip to Content

Hierarchical Test Application and Evaluation

0
Your rating: None
Author(s): 
- -, -, FR
(unregistered) Author(s): 
Zahra Najafi Haghi (University of Tehran)
Somayeh Sadeghi Kohan (University of Tehran)
Mohammadreza Najafi (University of Tehran)

We are presenting a package for testing system level designs. This package can be used to test a hybrid design consisting of gate level C++ codes and C++ complex functions as its processing elements, and TLM-2.0 transport interfaces as its communications. Our test utilities can be applied to communication channels and gate level parts simultaneous with simulation of high level C++ parts. Stuck-at, bridging and crosstalk fault models are considered for testing the gate level parts of a processing element or communications, while high level fault models are defined for testing high level communications.

Project Information
Project Acronym: 
ESL Design Methodology
Tag your tool
Keywords: 
test
c++
TLM
system level design
fault simulation
high-level fault model