Embedded Systems are built on top of SW and HW capabilities. It is economically convenient to exploit common HW solutions among different applications, through the use of platform based design and architectures based on configurable logic HW. A recurrent problem for the HW integrator is to validate a specific architecture without the knowledge of the final application(s). The development ofSW/HW co-simulation methods and related coverage metrics applied to this field are vital to achieve the verification of the embedded system platform. The verification framework is often constituted by a mixof SW, TLM, RTL. In this context the main goal of the VERTIGO project is the development of a systematic methodology to combine a simulation-based approach (dynamic verification) together with formal methods (static verification) integrated into an IP-cores and platform based design flow, for the purpose of producing a SW kit applied to the platform validation. Such system level based design verification flow must solve three main problems: •Verification of the correct interaction between all IP-cores and of the system in the networked environment, driven by coverage metrics •Production of a SW layer for the purpose of the embedded platform test •Verification of the correct modelling of system-level IP-cores and their correct mapping into RTL descriptions, driven by formal verification The solution of these problems require to correctly integrate verification and design into a robust flow, to smoothly move from verification languages (e.g., SystemC, System Verilog) to RTL languages, to combine dynamic and static verification techniques, thus exploiting and composing a variety of verification engines (e.g., SAT, High-Level Decision Diagrams, Hierarchical Petri Nets, EFSMs, etc.). VERTIGO addresses a new generation of technologies and tools for modelling and testing embedded platforms, that will be the foundation for a viable and cost-efficient mapping of HW/SW systems embedded in intelligent devices. The SYMBAD project aims at developing a system level design and verification platform for hardware and software integrated systems. The project will integrate in a system level design platform, a new formal verification technique (Linear Programming Validation) together with existing ones (SAT and Automatic Test Pattern Generation) and with a Property Coverage Checker. Such platform will lead to a new methodology in high-level system design offering conformance checking of low-level models with high level specifications. The SYMBAD platform and its verification techniques will be assessed on the design of a reconfigurable System-on-a-Chip (image processing system).Participants (Valiosys, INESC-ID and University of Verona) will provide the system design platform and verification tools while ST Microelectronics will be the user. OBJECTIVES The objectives of the SYMBAD project are to: - develop a system level design platform for hardware and software SoC systems including formal verification techniques, automatic test pattern generation and property coverage checking; - optimise design methodology with a validation process providing a joint use of 4 verification techniques integrated the high level design process; - assess the platform and the methodology with the design of a reconfigurable image processing system where the combinatorial complexity of reconfiguration makes simulation, testing and validation extremely difficult with existing techniques. The SYMBAD project will offer to SoC designers a complete system level design flow to model architectural, interfaces and communications between IP blocks and to verify conformance with high level specifications. The project starting point will be an existing system level design platform and prototype formal verification tools available from the partners. DESCRIPTION OF WORK The SYMBAD project will deliver- A system level design platform including formal verification facilities based on LPV and additional components offering supplementary formal verification tools: a test pattern generator, a property coverage checker and a formal verification engine based on a SAT solver- A corresponding methodology supporting the high level design and validation process integrated into the SYMBAD platform- A formally verified high level specification of a reconfigurable system. The main development activities will be on: - Development and integration of a System C front-end and communication libraries; - Development of an API for the formal verification tools; - Introduction of behavioural input in the LPV tool; - Integration of the LPV tool in the system level platform; - Development of additional integrated verification tools (a SAT solver, an ATPG tool and a property coverage checker); - Developing a visualisation tool to display the verification results- Developing a corresponding new system level design methodologyThe Work plan has been structured in five technical work packages, plus one for information dissemination, results exploitation planning and standardisation and a last one for project management. WP1: transferring existing formal verification techniques to the end-user and developing user requirements from this initial use. WP2: integrating the LPV tool inside the system level design platform, providing access for the test and evaluation of the tools from WP4. WP3: developing the system level design and verification platform specifications, including the System C entry language. In parallel, ST will also use the system level design platform to design its reconfigurable system. WP4: developing the formal verification tools from the other partners. WP5: validating the formal verification tools with the design of the reconfigurable system and finally by designing the corresponding new design methodology.