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CAERT - Compiler Assisted Energy Reduction Techniques for Embedded Processors

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Tool Name (abbreviation): 
CAERT
Author(s): 
Tohru Ishihara, K...
(unregistered) Author(s): 
Lovic Gauthier (Kyushu University)

Energy consumption is a fundamental barrier in taking full advantage of today and future semiconductor manufacturing technologies. The paper presents our recent research activities and results on characterizing and reducing the energy consumption in embedded systems. Firstly, a technique for characterizing the energy consumption of embedded processors during an application execution is presented. The technique trains a per-processor linear approximation model for fitting it to the energy consumption of the processor obtained by post-layout simulation. Secondly, based on the energy model mentioned above, the demonstration shows techniques for reducing the energy consumption by optimally mapping program code, stack frames and data items to the scratch-pad memory (SPM) of the processor memory space.

Project Information
Project Acronym: 
CREST ULP
Project Start: 
Sat, 10/01/2005
Project End: 
Thu, 03/31/2011
Project Description: 
The goal of the CREST ULP project is to develop hardware/software co-optimization techniques which minimize energy consumption of embedded systems by two orders of magnitude, while satisfying quality of services such as computational accuracy and reliability. Our research topics include energy characterization for embedded processor systems, compiler optimization for memory power reduction, multiprocessor RTOS with low-energy scheduling mechanisms, and so on. Partner Count: 1
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Keywords: 
Embedded System
Memory
compiler
energy consumption