One of the consequences of natural radiation (heavy ions, protons, neutrons) on integrated circuits is the modification of the content of memory cells also called Single Event Upset (SEU). A generic and flexible platform, the ASTERICS (Advanced System for the TEst under radiation of Integrated Circuits and Systems) tester, was developped at TIMA to be used both for radiation ground testing and fault injection experiments on complex digital circuits such as processors and FPGAs. A methodology to predict the sensitivity of a software application excecuted by a procesor will be presented and illustrated with results obtained on-line on a LEON3 processor. A SRAM board developped to perform real-life experiments devoted to put in evidence the sensitivity to SEUs of commercial SRAMs will also be presented and illustrated by results obtained when activating it during commercial flights and high altitude ballons